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Q&A: Ask the Expert
| Question: |
In our vendor supplied library, we don't have seperate isolation cells, so we will be using logic gates.
I assumed that we would need to use AND/NAND cells, but my collegue believes it is also possible to use NOR gates.
What is your opinion? |
| Submitter: |
Anonymous |
Answer: |
From a functional perspective, a NOR gate is feasible as an isolation cell. For example, an active high isolate_enable on one input could force a logic "0" on the output. However, if you are considering using standard cell logic for isolation, it is iimportant that it be properly characterized for the condition in which one of its inputs is unpowered, to ensure unintended behavior or electrical side effects will not occur.
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| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
07/09/2008 |
| Question: |
Hi,
WHat is the retention flop. What is the useo f that. When should i use that and why should i use htat. How retention mechanism is different from clamping the output of a shut down block.
Thanks |
| Submitter: |
Anonymous |
Answer: |
When power shutdown is employed on a logic block, the state of that logic will be lost when the power supply is removed, and must be reset when powered back up. However, a designer can choose to retain the state in one of several ways, such that the state can be restored when the logic is powered back up. One way of retaining state is to save of that state into memory prior to shutdown. Another method is to use retention flops instead of standard flops in the functional logic of the shutdown block.
Retention flops are functionally the same as standard flops, but have a primary and secondary power supply, and additional control input(s) for indicating whether the flop should be in retention mode. Retention flops are designed to hold their state (i.e., last known valid value) when primary power is turned off. In normal operational mode, when the primary power supply is available, a retention flop behaves like a standard flop. When the primary power goes away, the secondary (or "backup") power pin will provide enough power for the retention flop to maintain its state. However, it is not designed to drive out that state when in shutdown mode, only to maintain it internally. When primary power is restored, and the "restore" signal to the retention flop is activated, the retention flop will resume driving its saved state.
A "latch type" isolation cell does hold its state when isolation is enabled; however, it differs from a retention flop, because it is designed to stay actively driving its known value while isolation is enabled. Latch type isolation cells would only be used on the outputs of a logic block being shutdown, whereas retention flops would be used within the logic of that shutdown block. |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
07/09/2008 |
| Question: |
In power island flow, we will avoid adding buffers on isolation input net in alwayson. what is the reason for it. |
| Submitter: |
Anonymous |
Answer: |
In a power domain (also known as a power island) that is to be shutdown, there may be some logic that must remain active during shutdown, such as the control signals for retention registers or isolation cells. Those signals are referred to as "always-on". If the fanout of those always-on signals requires buffering within the shutdown power domain, it is essential for the buffers inserted on those signals to be powered by an alternate power supply, such that they will remain powered when the primary power is turned off. We refer to those buffers as "always-on". |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
07/09/2008 |
| Question: |
Hi,
what are the pros and cons of powergating versus retention flop usage in a design.
1) when should i go for power gating
2) When should i go for retention flop
3) can i go for both
Thanks |
| Submitter: |
Anonymous |
Answer: |
Power gating, also known as power shutdown, is the technique of removing power from certain blocks of logic, referred to as power domains. It is an advanced low power technique for used significantly reducing leakage power when the logic is inactive.
When a power domain is shut down, the logic in that power domain will lose its state unless some form of state retention is employed. One method for retaining the state is to use retention flops for the sequential elements within the shutdown power domain, such that when primary power is turned off, the retention flops (powered with a backup power supply) will hold their last known state and restore that state when the power domain comes out of shutdown mode. |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
07/09/2008 |
| Question: |
why use isolation cell in chip? If isolation cell not used when power down, what will happen to logic block which is always power-on ? |
| Submitter: |
Anonymous |
Answer: |
It is generally recommended that isolation cells be used for all signals that are driven from a powered-down block to a powered-up (i.e., always-on) block. This allows the signals to be driven to a known state when the driving block is powered down. If isolation cells are not used, those signals will be driving unknown values into the powered-up block, possibly corrupting the state of that block.
Isolation cells can drive a logic '1', logic '0', or last known value during isolation, depending on which type you define in your power intent. |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
03/19/2008 |
| Question: |
Hi,
I have a power down block in my chip. How do i findout the number of power switches(power gating) needed for that block. The freq of the block is 210 MHZ. what are the all the parameters needed to find out the number of power switches for a given block. |
| Submitter: |
Anonymous |
Answer: |
Answer: In order to determine the number of power switches necessary for your shutdown block, you need to run an analysis of the power network (PNA), considering the power consumption of the cells in your design. The analysis will determine the amount of IR drop that occurs in your design, across the area of the shutdown block. You decide how many switches are necessary, and in what topology, based on what IR drop is acceptable for your design and what amount of area you can allow to be consumed by the power switches. For more accurate analysis, you will want to use vector-based power consumption input, instead of area-based statistical data.
Note:
Synopsys provides power network analysis and power switch topology exploration in its IC Compiler tool, using the "analyze_fp_rail" and "explore_header_footer" commands, respectively. |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
03/19/2008 |
| Question: |
Hi,
i understand we need to use Level Shifter when we go from low voltage domain to High Voltage domain.(Up shifter) and we do not need any shifter when we go from High to Low domain. Then what is the purpose of designing a low level shifter or when do we use Low level shifter. |
| Submitter: |
Anonymous |
Answer: |
You are correct in that it is not electrically necessary to have a high-to-low level shifter, since overdriving the input to a lower voltage cell won't cause electrical problems such as crowbar switching current. However, if the library cells are not characterized for this wider input voltage swing, it can affect the accuracy of your static timing analysis, since the tool will need to extrapolate. So if you do not have this characterization for your library cells, then you should insert high-to-low level shifters.
Chapter 3 of the "Low Power Methodology Manual" covers the topic of level shifting in detail. This tool-agnostic reference document is available for download from the Synopsys web site at: www.synopsys.com/lpmm |
| Responder: |
Josefina Hobbs - MBD |
| Post Date: |
10/10/2007 |
| Question: |
Hello sir,
Worst case timing is traditionally modeled using low voltage, slow process and high temperature. Nanometer technologies exhibit inverted temperature behavior, where worst timing is achieved at low voltage, slow process and low temperature.
Can you please explain the concept of TEMPERTURE INVERSION in nanometer designs ? |
| Submitter: |
Anonymous |
Answer: |
Temperature inversion is a phenomenom of 90nm and below technologies where delay and voltage invert their relationship. With older process nodes, delay increases as the temperature increases. At 90nm and below, at a certain voltage, delays decrease as temperature increases.
At 90nm and below, usage of high- and low-Vt process options is prevalent due to the leakage savings and preformance they provide. Advance process technologies also support lower Vdd. The combination of low/high-Vt with lower Vdd results in the temperature inversion phenomenom where the difference between Vdd and Vt is much smaller than with previous generations of process technologies.
Delay is an inverse function of saturated current which increases linearly with carrier mobility and quadratically with voltage (Vdd-Vt). Due to opposite temperature sensititives of mobility and threshold voltages, the current delivered experiences this inversion which in turn affects the delay.
As a result, most cell library vendors now include temperature inversion corner(s) in addition to the standard PVT corners. |
| Responder: |
Mary Ann White - MBD |
| Post Date: |
09/19/2007 |
| Question: |
Is the isolation cell different than a nand cell? |
| Submitter: |
Anonymous |
Answer: |
Isolation cells are electrically different from NAND gates. Isolation cells are used between power domains to prevent propagation of unknown signals from a power-gated domain (e.g. shut-down) into an always-on powered domain.
Typically, the input drive of an isolation cells is different than that of a NAND gate. Library vendors that supply low power libraries will supply isolation cells or, in some case, level shifters with built-in isolation capabilities.
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| Responder: |
Mary Ann White - MBD |
| Post Date: |
08/03/2007 |
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