Resource Center: Articles

A Ticking Time Bomb? Chip Design Magazine - Srikanth Jadcherla (Synopsys) May 22, 2008	READ
Static Checks for Power Management at RTL EDA DesignLine - Krishna Balachandran (Synopsys) May 20, 2008	READ
Voltage-aware simulation: No longer a fad, but a must for low-power designers EDN - Krishna Balachandran (Synopsys) May 14, 2008	READ
Architectural Issues for Power Gating Portable Design - Mike Keating, Alan Gibbons, Kaijian Shi (Synopsys), David Flynn and Robert Aiken (ARM) April 8, 2008	READ
'Off by Design' architectures curb energy waste SCDsource - Srikanth Jadcherla March 25, 2008	READ
Perform low power manufacturing test, part 2 EETimes-Asia, Chris Allsup February 1, 2008	READ
Perform low power manufacturing test, part 1 EETimes-Asia, Chris Allsup Jan 16-31, 2008	READ
Why Power Standards Matter EETimes-Europe, Larry Vivolo January 14 – February 3, 2008	READ
Design Tools Now Embrace Power Consciousness Power Systems Design Europe: Mary Ann White Jan/Feb 2008	READ
Low Power Methodology Manual for System-on-Chip Design Electronic Design, Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi January 7, 2008	READ
Strengthening the Design System Through Interoperability Chip Design Magazine Oct/Nov 2007	READ
Low Power Design For Analog/Mixed-Signal IP EDA DesignLine - Navraj Nandra – March 4, 2008	READ
Detecting Leakage Problems in Low-Power Designs Nikkei Electronics Asia –Mike Demler – 9/07 There is increasing pressure on designers to incorporate low-power techniques in order to meet the rapidly growing demand for battery-operated, portable consumer electronics devices. At the same time, migration of semiconductor processes to 65nm and below has changed device physics such that controlling leakage is the major challenge for all designers working in advanced nanometer technologies. Dynamic simulation can fail to detect high current paths that result from errors in power-management circuitry that is intended to perform leakage control. To address this verification gap, a new set of solutions for vectorless transistor-level analysis of power-down circuits and leakage paths has been developed and is discussed in this article.	READ
The Unified Power Format - A Standard Done the Right Way Chip Design Magazine – Karen Bartleson – August/September 2007 Karen Bartleson, Director of Interoperability at Synopsys, discusses the development of the Unified Power Format (UPF) and the standard’s benefits to the designer.	READ
Practical Power Network Synthesis For Power-Gating Designs EDA DesignLine - Kaijian Shi, Zhian Lin, Yi-Min Jiang - 6/5/2007 Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.	READ
Designs that improve performance per watt Power Management DesignLine - Tim Higgs, Erik Peter, Henry Wong and Jim Kardach - 3/26/2007 In recent years, advances have been made that dramatically improve efficiency in computer systems, as well as reducing current leakage and varying energy consumption according to demand. This article examines developments in designs to increase performance per watt.	READ
Integrating Power Awareness into IC Design EDA Design Line - Toshiyuki Saito - 3/1/2007 Several industry-wide efforts are being made to achieve a common means to integrate low-power-related design features into IC design flows. This article offers ways to achieve competitive low power capabilities in design flows.	READ
New EDA Tools Improve Low Power Design EDA Design Line - Dave Allen - 2/19/2007 Ten years ago, power was a minor concern for many IC designers. Today, four out of five chips have a power budget below 2W. The emphasis on low power is affecting all designers, but fortunately low power EDA tools can improve design flow.	READ
Unified Power Format lowers power consumption in SoCs EE Times - Mike Keating - 2/12/2007 Read this article to see how key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions.	READ
Save Those Watts With A Power-Aware Design Flow For SoC Electronic Design - Mohit Bhatnagar, Jack Erickson, Anand Iyer and Pete McCrorie - 7/6/2006 Low power must be taken into consideration as early in the design flow process as possible. This article examines potential shortfalls in considering low power post-mortem-and how you can design with an emphasis on low power from the beginning of a project.	READ
Running start helps clear 90-nm hurdles EE Times - Richard Goering - 4/3/2006 In 2006, it was projected that 32 percent of ASIC starts were at 90 nm. As 90 nm increasingly becomes mainstream, as evidenced by increase tape-out success, many designers are familiar are well-known techniques for managing power concerns. However, there are still untold costs of low power design. See the facts in this article and how you can remove potential design hurdles.	READ
Leakage takes priority at 65 nm EE Times - Richard Goering - 1/16/2006 As the first reports on 65-nanometer design come in from the field, the good news is that there don't appear to be any problems at 65 nm that weren't there at 90. The bad news is that some of the problems that plagued 90 nm get much worse at the new node. Get the whole story in this article.	READ
Low-power flow enables multi-supply voltage ICs EE Times - Robert Aitken, George Kuo and Ed Wan - 3/21/2005 Designers face a continuing struggle in balancing power and performance in leading-edge system-on-chip (SoC) designs. This article examines these fundamental concerns and offers insights into key low power areas such as battery life span and dynamic power reduction.	READ