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Functional Verification
There are huge challenges involved in designing and verifying multi-million gate chips. Engineers have little room for error when dealing with multiple processors, complex peripheral interfaces and millions of lines of code. Every time the number of gates on a chip doubles, the required verification effort quadruples. Our online community, SynopsysOC, brings together engineers with the common aim of sharing information and resources to drive verification solutions forward.
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SynopsysOC Discussion Forum
an open community where low power and verification design challenges are discussed.
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| VMM for SystemVerilog Companion Guide |
 VMM for SystemVerilog Companion Guide is a handy quick reference for users of the Verification Methodology Manual (VMM) for SystemVerilog, a professional book co-authored by verification experts from ARM Ltd and Synopsys, Inc and published by Springer Science and business media. DOWNLOAD
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| Featured Functional Verification Video |
 DesignWare VIP Detailed Usage
Presenter: Darrin Mossor, Synopsys
The Synopsys DesignWare Verification IP for AMBA 3 AXI provides an effective method of verifying AMBA 3 AXI protocol based designs. This session provides in-depth technical insight into working with the Verification Methodology Manual for SystemVerilog compliant and “AMBA 3 Assured” DesignWare Verification IP. The DesignWare Verification IP for AMBA 3 AXI includes master, slave, monitor and verification interconnect components with each supporting all the AMBA 3 AXI address, data widths, and protocol transfer and response types. The session documents how this full featured command set can be utilized to create both a directed test transaction environment as well as how to leverage the coverage driven, constrained random verification interface support.
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| Book Club Verification Methodology Manual |
 Verification Methodology Manual for SystemVerilog
The Verification Methodology Manual for SystemVerilog is a blueprint for system-on-chip (SoC) verification success. The book documents advanced functional verification techniques used by industry experts to validate complex SoCs.
Go to the SynopsysOC Forum to discuss the VMM manual.
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